According to a recent analysis by Bryan Lewis and John Barber, ASIC Design Starts dropped by more than 50% between 2000 and 2008.
ASIC Design Starts Dropping: Implications for EDA
I attended a very thought provoking talk tonight on “Factors Influencing IC Design Starts and Future Revenues” by Bryan Lewis and John Barber of Gartner at the Santa Clara Valley Chapter of the IEEE Components, Packaging & Manufacturing Technology Society. Bryan and John declined to make their slides available but I was able to crib this chart from an EE Times article “Sockets scant for costly ASICs”
| 2000 | 2005 | 2006 | 2007 | 2008 |
| 7,749 | 3,623 | 3,391 | 3,196 | 3,048 |
Chip volume and complexity combine to increase total revenues. The design start trend has clear implications for an EDA industry that in the 80s and 90s saw ASICs (gate array and standard cells) as key drivers. The other interesting trend is that process lifetimes are elongating considerably. The need to move to a new process was another strong driver in the 90s, as deep submicron and very deep submicron processes required entirely new back-end tool sets to model their complexities and constraints accurately. This is a trend that has been underway for more than a decade, as the EE Times article points out.
Back in the mid-1990s, any given year saw a total of some 10,000 ASIC design starts, according to iSuppli. A design start is equal to a unique tapeout, but the IC may or may not go into production, Gartner’s Lewis said.
It would seem that the near term EDA opportunities may have more to do with complexity management as complexity continues to increase, and intelligent management and recycling of legacy design data.